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page 1 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet the digital tomodachi series of non-isolated dc-dc converters deliver exceptional electrical and thermal performance in dosa based footprints for point-of-load converters. operating from a 4.5vdc-14.4vdc input, thes e are the converters of choice for intermediate bus architecture (iba) and distributed power architecture applications that require high efficiency, tight regulation, and high reliability in elevated tem perature environments with low airflow. the pmbus in terface supports a range of commands to both control and monitor the module. the module also includes the tunable loop? feature that allows the user to optimize the dynamic response of the converter to match the load with reduced amount of output capacitance leading to savings on cost and pwb area. the fgld12sr6040*a converter of the tomodachi series delivers 40a of out put current at a tightly regulated programmable and pmbus control output voltage of 0.45vdc to 2.0vdc. the thermal performance of the fgld12sr6040*a is best-in-class: little derating is needed up to 85 , under natural convection. applications ? intermediate bus architecture ? telecommunications ? data/voice processing ? distributed power architecture ? computing (servers, workstations) ? test equipments features ? compliant to rohs eu ? directive 2011/65/eu ? delivers up to 40a (80w) ? high efficiency, no heatsink required ? negative and positive on/off logic ? dosa based ? small size: 33.02 x 13.46 x 10.9mm (1.3 in x 0.53 in x 0.429 in) ? tape & reel packaging ? programmable output voltage from 0.6v to 2.0v via external resistor. digitally adjustable down to 0.45vdc ? digital interface through the pmbus? # protocol ? tunable loop? to optimize dynamic output voltage response ? flexible output voltage sequencing ez-sequence ? power good signal ? fixed switching frequen cy with capability of external synchronization ? auto-reset output over-current protection ? remote on/off ? ability to sink and source current ? no minimum load required ? start up into pre-biased output ? ul * 60950-1 2 nd ed. recognized, csa ? c22.2 no. 60950-1-07 certified, and vde ? (en60950-1 2 nd ed.) (pending) ? iso** 9001 and iso 14001 certified manufacturing facilities * ul is a registered trademark of u nderwriters laboratories, inc. ? csa is a registered trademark of canadian standards association. ? vde is a trademark of verband de utscher elektrotechniker e.v. ** iso is a registered trademark of the in ternational organization of standards # the pmbus name and logo are registered trademarks of the system management interface forum (smif)
page 2 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet absolute maximum ratings stresses in excess of the absolute maximum ratings ma y lead to degradation in performance and reliability of the converter and may result in permanent damage. electrical specifications all specifications apply over specif ied input voltage, output load, and temper ature range, unless otherwise noted. parameter notes min typ max units absolute maximum ratings 1 input voltage continuous -0.3 15 vdc seq, sync, vs+ 7 vdc clk, data, smbalert 3.6 vdc operating temperature ambient temperature -40 85 c storage temperature -55 125 c output voltage 0.45 2.0 vdc parameter notes min typ max units input characteristics operating input voltage range 4.5 14.4 vdc maximum input current vin=4.5v to 14v, io-max 24 adc input no load current vout=2.0v 104 ma vout=0.6v 54.7 ma input stand-by current vin=12v, module disabled 16.4 ma inrush transient, i 2 t 1 a 2 s input reflected-ripple current peak-to-peak (5hz to 20mhz, 1uh source impedance; vin=0 to 14v, io-max 90 map-p input ripple rejection (120hz) -60 db input under voltage lockout turn-on threshold 3.25 vdc turn-off threshold 2.6 vdc hysteresis 0.25 vdc pmbus adjustable input under voltage lockout thresholds 2.5 14 vdc resolution of adju stable input under voltage threshold 500 mv
page 3 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet electrical specifications (continued) parameter notes min typ max units output characteristics output voltage set point with 0.1% tolerance for external resistor used to set output voltage -1.0 +1.0 %vout output voltage range (over all operating input voltage, resistive load and temperature conditions until end of life) -3.0 +3.0 %vout adjustment range (selected by an external resistor) some output voltages may not be possible depending on the input voltage ? see feature description section 0.6 2.0 vdc pmbus adjustable output voltage range -25 +25 %vout pmbus output voltage adjustm ent step size 0.4 %vout remote sense range 0.5 vdc output regulation line (vin = min to max) 6 mv load (io = min to max) 10 mv temperature (tref=min to max) 0.4 %vout output ripple and noise vin=12v, io= min to max, co = 0.1uf+22uf ceramic capacitors peak to peak 5mhz to 20mhz bandwidth 50 100 mvp-p rms 5mhz to 20mhz bandwidth 20 38 mvrms external load capacitance 1 plus full load (resistive) % without the tunable loop esr 1m ? 6x47 6x47 uf with the tunable loop esr 0.15m ? 6x47 7,000 uf esr 10m ? 6x47 8,500 uf output current range (in either sink or source mode) 0 40 adc output current limit inception (hiccup mode) current limit does not operate in sink mode 150 % io-max output short-circuit current vo 250mv, hiccup mode 2..1 arms efficiency vin = 12vdc, ta = 25c, io = max vout=1.8vdc 91.5 % vout=1.2vdc 88.5 % vout=0.6vdc 81.3 % 1 external capacitors may requi re using the new tunable loop tm feature to ensure that the module is stable as well as getting the best transient response. see the tunable loop tm section for details.
page 4 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet electrical specifications (continued) general specifications feature specifications parameter notes min typ max units switching frequency 400 khz frequency synchronization synchronization frequency range 350 480 khz high level input voltage 2.0 v low level input voltage 0.4 v input current, sync 100 na minimum pulse width, sync 100 ns maximum sync rise time 100 ns parameter notes min typ max units calculated mtbf io = 0.8 * io-max, ta = 40c telecordia issue 2 method 1 case 3 6,498,438 hours weight 11.7(0.41) g (oz.) parameter notes min typ max units on/off signal interface vin = min to max, open collector or equivalent, signal reference to gnd positive logic logic high (module on) input high current 10 ua input high voltage 3.5 vin-max v logic low (module off) input low current 1 ma input low voltage -0.3 0.4 v negative logic on/off pin is open collect or/drain logic input with external pull-up resistor; signal reference to gnd logic high (module off) input high current 1 ma input high voltage 2 vin-max v logic low (module on) input low current 10 ua input low voltage -0.2 0.4 v
page 5 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet feature specifications * over temperature warning ? warning may not activate before alarm and unit may shutdown before warning. parameter notes min typ max units turn-on delay and rise time vin = vin-nom, io = io-max , vo to within 1% of steady state case 1: on/off input is enabled and then input power is applied delay from instant at which vin = vin-min until vo = 10% of vo-set) 1.1 ms case 2: input power is applied for at least one second and then the on/off input is enabled delay from instant at which von/off is enabled until vo = 10% of vo-set 700 us output voltage rise time time for vo to rise fr om 10% of vo-set to 90% of vo-set 1.5 ms output voltage overshoot with or without maximum external capacitance ta = 25 o c, vin = vin-min to vin-max, io = io-min to io-max 3.0 %vout over temperature protection (see thermal considerations section) 145 c pmbus over temperature warning threshold * 130 c tracking accuracy vin-min to vom-max, io-min to io-max, vseq < vo power-up: 0.5v/ms 100 mv power-down: 0.5v/ms 100 mv input under voltage lockout turn-on threshold 4.25 vdc turn-off threshold 3.96 vdc hysteresis 0.25 vdc pmbus adjustable input under voltage lockout thresholds 2.5 14 vdc resolution of adju stable input under voltage threshold 500 mv pgood (power good) signal interface open drain, vsupply ? 5vdc overvoltage threshold for pgood on 108 %vout overvoltage threshold for pgood off 110 %vout undervoltage threshold for pgood on 92 %vout undervoltage thre shold for pgood off 90 %vout pulldown resistance of pgood pin 50 ? sink current capability into pgood pin 5 ma
page 6 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet digital interface specifications parameter notes min typ max units pmbus signal interface characteristics input high voltage (clk, data) 2.1 3.6 v input low voltage (clk, data) 0.8 v input high level current (clk, data) -10 10 ua input low level current (clk, data) -10 10 ua output low voltage (clk, data, smbalert#) i out =2ma 0.4 v output high level open drain leakage current (data, smbalert#) v out =3.6v 0 10 ua pin capacitance 0.7 pf pmbus operating frequency range slave mode 10 400 khz data hold time receive mode 0 ns transmit mode 300 ns data setup time 250 ns measurement system characteristics read delay time 153 192 231 us output current measurement range 0 40 a output current measurement resolution 62.5 ma output current measurement gain accuracy (at 25c) 5 % output current measurem ent offset 0.1 a vout measurement range 0 2.0 v vout measurement resolution 16.25 mv vout measurement gain accuracy -2 2 lsb vout measurement offset -3 3 lsb vout measurement accuracy 70 mv vin measurement range 0 14.4 v vin measurement resolution 32.5 mv vin measurement gain accuracy -2 2 lsb vin measurement offset -5.5 1.4 lsb vin measurement accuracy 3 %
page 7 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet design considerations input filtering the fgld12sr6040*a converter should be connected to a low ac-impedance source. a highly inductive source can affect the stability of the module. an input capacitance must be placed directly adjacent to the input pin of the module, to minimize input ripple voltage and ensure module stability. to minimize input voltage ripple, ceramic capacitors are recommended at the input of the module. fig-1 shows the input ripple voltage for various output voltages at 40a of load current with 4x47uf, 6x47uf or 8x47uf ceramic capacitors and an input of 12v. output filtering the fgld12sr6040*a is designed for low output ripple voltage and will meet the maximum output ripple specification with 0.1uf ceramic and 47uf ceramic capacitors at the output of the module. however, additional output filtering may be required by the system designer for a number of reasons. first, there may be a need to further reduce the output ripple and noise of the module. second, the dynamic response characteristics may need to be customized to a particular load step change. to reduce the output ripple and improve the dynamic response to a step load change, additional capacitance at the output can be used. low esr polymer and ceramic capacitors are recommended to improve the dynamic respons e of the module. fig-2 provides output ripple information for different external capacitance values at various vo and a full load current of 40a. for stable operation of the module, limit the capacitance to less than the maximum output capacitance as specified in the electrical specification table. optimal performance of the module can be achieved by using the tunable loop? feature described later in this data sheet. safety consideration for safety agency approval the power module must be installed in compliance with the spacing and separation requirements of the end-use safety agency standards, i.e., ul 60950-1 2nd, csa c22.2 no. 60950-1-07, din en 60950-1:2006 + a11 (vde0805 teil 1 + a11):2009-11; en 60950-1:2006 + a11:2009-03. (pending) for the converter output to be considered meeting the requirements of safety extra-low voltage (selv), the input must meet selv requirements. the power module has extra-low voltage (elv) outputs when all inputs are elv. the input to these units is to be provided with a fast acting fuse with a maximum rating of 30a, 100v (for example, littlefuse 456 series) in the positive input lead. . fig-1: input ripple voltage for various output voltages with various external ceramic capacitors at the input (40a load). input voltage is 12v. scope bandwidth limited to 20mhz. 50 100 150 200 250 300 350 400 0.6 0.8 1 1.2 1.4 1.6 1.8 2 ripple voltage (mvpk-pk) output voltage (volts) 4x22uf ext cap 6x22uf ext cap 8x22uf ext cap fig-2: output ripple voltage for various output voltages with external 6x47uf, 8x47uf or 10x47uf ceramic capacitors at the output (40a load). input voltage is 12v. scope bandwidth limited to 20mhz. 0 10 20 30 40 0.6 0.8 1 1.2 1.4 1.6 1.8 2 ripple (mvp-p) output voltage(volts) 6x47uf ext cap 8x47uf ext cap 10x47uf ext cap
page 8 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet analog feature descriptions remote on/off the module can be turned on and off either by using the on/off pin (analog interface) or through the pmbus interface (digital). the module can be configured in a number of ways through the pmbus interface to react to the two on/off inputs: ? module on/off can be controlled only through the analog interface (digital interface on/off commands are ignored) ? module on/off can be controlled only through the pmbus interface (analog interface is ignored) ? module on/off can be controlled by either the analog or digital interface the default state of the module (as shipped from the factory) is to be controlled by the analog interface only. if the digital interface is to be enabled, or the module is to be controlled only through the digital interface, this change must be made through the pmbus. these changes can be made and written to non-volatile memory on the module so that it is remembered for subsequent use. analog on/off the fgld12sr6040*a power modules feature an on/off pin for remote on/off operation. two on/off logic options are available. in the positive logic on/off option, (device code suffix ?p? - see ordering information), the module turns on during a logic high on the on/off pin and turns off during a logic low. with the negative logic on/off option, (device code suffix ?n? - see ordering information), the module turns off during logic high and on during logic low. the on/off signal should be always referenced to ground. for either on/off logic option, leaving the on/off pin disconnected will turn the module on when input voltage is present. for positive logic modules, the circuit configuration for using the on/off pin is shown in fig-3. for negative logic on/off modules, the circuit configuration is shown in fig-4. digital on/off please see the digital feature descriptions section. monotonic start-up and shut-down the module has monotonic start-up and shutdown behavior for any combination of rated input voltage, output current and operatin g temperature range. startup into pre-biased output the module can start into a prebiased output as long as the prebias voltage is 0.5v less than the set output voltage. fig-3: circuit configuration for using positive on/off logic. module internal pullup on/off i 10k pwm enable 470 on/off q1 gnd vin+ on/off 10k rpullup cr1 + _ v fig-4: circuit configuration for using negative on/off logic. pwm enable vin+ internal pullup 22k _ on/off v rpullup on/off module q1 + q3 10k i 470 gnd 10k 22k on/off
page 9 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet analog output volt age programming the output voltage of the module is programmable to any voltage from 0.6dc to 2.0vdc by connecting a resistor between the trim and sig_gnd pins of the module. certain restrict ions apply on the output voltage set point depending on the input voltage. these are shown in the output voltage vs. input voltage set point area plot in fig-5. the upper limit curve shows that for output voltages lower than 1v, the input voltage must be lower than the maximum of 14.4v. the lower limit curve shows that for output voltages higher than 0.6v, the input voltage needs to be larger than the minimum of 4.5v. without an external resistor between trim and sig_gnd pins, the output of the module will be 0.6vdc. to calculate the value of the trim resistor, rtrim for a desired output voltage, should be as per the following equation: rtrim is the external resistor in kohm vo-req is the desired output voltage note that the tolerance of a trim resistor will affect the tolerance of the output voltage. standard 1% or 0.5% resistors may suffice for most applications; however, a tighter tolerance can be obtained by using two resistors in series instead of one standard value resistor. table 1 provide rtrim values required for some common output voltages. table 1: trim resistor value v o-reg [v] r trim [k ? ] 0.6 open 0.9 40 1.0 30 1.2 20 1.5 13.33 1.8 10 digital output voltage adjustment please see the digital feature descriptions section. remote sense the power module has a remote sense feature to minimize the effects of distribution losses by regulating the voltage between the sense pins (vs+ and vs-). the voltage drop between the sense pins and the vout and gnd pins of the module should not exceed 0.5v. analog voltage margining output voltage margining can be implemented in the module by connecting a resistor, rmargin-up, from the trim pin to the ground pin for margining-up the output voltage and by connecting a resistor, rmargin-down, from the trim pin to output pin for margining-down. fig-7 shows the circuit configuration for output voltage margining. the pol programming tool, available at www.fdk.com under the downloads section, also calculates t he values of rmargin-up and rmargin-down for a specific output voltage and % margin. please consult your local fdk fae for additional details. ] k [ 0.6) - (v 12 r req - o trim ? fig-6: circuit configuration for programming output voltage using an external resistor. caution ? do not connect sig_gnd to gnd elsewhere in the layout. fig-5: output voltage vs. input voltage set point area plot showing limits where the output voltage can be set for different input voltages.
page 10 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet digital output voltage margining please see the digital feature descriptions section. output voltage sequencing the power module includes a sequencing feature, ezsequence that enables users to implement various types of output voltage sequencing in their applications. this is accomplished via an additional sequencing pin. when not using the sequencing feature, leave it unconnected. the voltage applied to the seq pin should be scaled down by the same ratio as used to scale the output voltage down to the reference voltage of the module. this is accomplished by an external resistive divider connected across the sequencing voltage before it is fed to the seq pin as shown in fig-8. in addition, a small capacitor (suggested value 100pf) should be connected across the lower resistor r1. for all tomodachi modules, the minimum recommended delay between the on/off signal and the sequencing signal is 10ms to ensure that the module output is ramped up according to the sequencing signal. this ensures that the module soft-start routine is completed before the sequencing signal is allowed to ramp up. when the scaled down sequencing voltage is applied to the seq pin, the output voltage tracks this voltage until the output reaches t he set-point voltage. the final value of the sequencing voltage must be set higher than the set-point voltage of the module. the output voltage follows the sequencing voltage on a one-to-one basis. by connecting multiple modules together, multiple modules can track their output voltages to the voltage applied on the seq pin. the module?s output can track the seq pin signal with slopes of up to 0.5v/msec during power-up or power-down. to initiate simultaneous shutdown of the modules, the seq pin voltage is lowered in a controlled manner. the output voltage of the modules tracks the voltages below their set-point voltages on a one-to-one basis. a valid input voltage must be maintained until the tracking and output voltages reach ground potential. note that in all digital tomodachi series of modules, the pmbus output undervoltage fault will be tripped when sequencing is employed. this will be detected using the status_word and status_vout pmbus commands. in addition, the smbalert# signal will be asserted low as occurs for all faults and warnings. to avoid the module shutting down due to the output undervoltage fault, the module must be set to continue operation without interruption as the response to this fault (see the description of the pmbus command vout_uv_fault_response for additional information). fig-7: circuit configuration for margining output voltage. fig-8: circuit showing connection of the sequencing signal to the seq pin.
page 11 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet over-current protection to provide protection in a fault (output overload) condition, the unit is equipped with internal current-limiting circuitry and can endure current limiting continuously. at t he point of current-limit inception, the unit enters hiccup mode. the unit operates normally once the output current is brought back into its specified range. digital adjustable overcurrent warning please see the digital feature descriptions section. over-temperature protection to provide protection in a fault condition, the unit is equipped with a thermal shutdown circuit. the unit will shut down if the over-tem perature threshold of 145oc (typ) is exceeded at the thermal reference point tref. once the unit goes into thermal shutdown it will then wait to cool before attempting to restart. digital temperature status via pmbus please see the digital feature descriptions section. digitally adjustable ou tput over and under voltage protection please see the digital feature descriptions section. input under-voltage lockout (uvlo) at input voltages below the input under-voltage lockout limit, the module operation is disabled. the module will begin to operate at an input voltage above the under-voltage lockout turn-on threshold. digitally adjustabl e input undervoltage lockout please see the digital feature descriptions section. digitally adjustable po wer good thresholds please see the digital feature descriptions section. synchronization the module switching frequen cy can be synchronized to a signal with an external frequency within a specified range. synchronization can be done by using the external signal applied to the sync pin of the module as shown in fig-9, with the converter being synchronized by the ri sing edge of the external signal. the electrical specifications table specifies the requirements of the external sync signal. if the sync pin is not used, the module should free run at the default switching frequency. if synchronization is not being used, connect the sync pin to gnd . paralleling with active load sharing (-p option) for additional power requirements, the fgld12sr6040*a power module is also equipped with paralleling capability. up to five modules can be configured in parallel, with active load sharing. to implement paralleling, the following conditions must be satisfied. ? all modules connected in parallel must be frequency synchronized where they are switching at the same frequency. this is done by using the sync function of the module and connecting to an external frequency source. modules can be interleaved to reduce input ripple/filtering requirements. ? the share pins of all units in parallel must be connected together. the path of these connections should be as direct as possible. ? the remote sense connections to all modules should be made that to the same points for the output, i.e. all vs+ and vs- terminals for all modules are connected to the power bus at the same points. some special considerations apply for design of converters in parallel operation: ? when sizing the number of modules required for parallel operation, take note of the fact that current sharing has some tolerance. in addition, under transient conditions such as a dynamic load change and during startup, all converter output currents will not be equal. to allow for fig-9: external source connections to synchronize switching fr equency of the module.
page 12 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet such variation and avoid the likelihood of a converter shutting off due to a current overload, the total capacity of the paralleled system should be no more than 90% of the sum of the individual converters. as an example, for a system of four fgls converters in parallel, the total current drawn should be less that 90% of (3 x 40a), i.e. less than 108 a. similarly, four units can support a load less than 144a. ? all modules should be turned on and off together. this is so that all modules come up at the same time avoiding the problem of one converter sourcing current into the other leading to an overcurrent trip condition. to ensure that all modules come up simultaneously, the on/off pins of all paralleled converters should be tied together and the converters enabled and disabled using the on/off pin. note that this means that converters in parallel cannot be digitally turned on as that does not ensure that all modules being paralleled turn on at the same time. ? if digital trimming is used to adjust the overall output voltage, the adjustments need to be made in a series of small steps to avoid shutting down the output. each step should be no more than 20mv for each module. for example, to adjust the overall output voltage in a setup with two modules (a and b) in parallel from 1v to 1.1v, module a would be adjusted from 1.0 to 1.02v followed by module b from 1.0 to 1.02v, then each module in sequence from 1.02 to 1.04v and so on until the final output voltage of 1.1v is reached. ? if the sequencing function is being used to start-up and shut down modules and the module is being held to 0v by the tracking signal then there may be small deviations on the module output. this is due to controller duty cycle limitations encountered in trying to hold the voltage down near 0v. ? the share bus is not designed for redundant operation and the system will be non-functional upon failure of one of the units when multiple units are in parallel. in particular, if one of the converters shuts down dur ing operation, the other converters may also shut down due to their outputs hitting current limit. in such a situation, unless a coordinated restart is ensured, the system may never properly restart since different converters will try to re start at different times causing an overload condition and subsequent shutdown. this situation can be avoided by having an external output voltage monitor circuit that detects a shutdown condition and forces all converters to shut down and restart together. when not using the active load share feature, share pins should be left unconnected. measuring output current, output voltage and input voltage please see the digital feature descriptions section. dual layout identical dimensions and pin layout of analog and digital tomodachi modules permit migration from one to the other without needing to change the layout. in both cases the trim resistor is connected between trim and signal ground. power good the module provides a power good (pgood) signal that is implemented with an open-drain output to indicate that the output voltage is within the regulation limits of the power module. the pgood signal will be de-asserted to a low state if any condition such as overtemperature, overcurr ent or loss of regulation occurs that would result in the output voltage going 10% outside the setpoi nt value. the pgood terminal can be connected through a pullup resistor (suggested value 100k ? ) to a source of 5vdc or lower. tunable loop? the module has a feature t hat optimizes transient response of the module called tunable loop? external capacitors are us ually added to the output of the module for two reasons: to reduce output ripple and noise (see fig-2) and to reduce output voltage deviations from the steady-state value in the presence of dynamic load current changes. adding external capacitance however affects the voltage control loop of the module, typically causing the loop to slow down with sluggish response. larger values of external capacitance could also cause the module to become unstable. the tunable loop? allows the user to externally adjust the voltage control loop to match the filter network connected to the output of the module. the tunable loop? is implemented by connecting a series r-c between the sense and trim pins of the module, as shown in fig-10. this r-c allows the user to externally adjust the voltage loop feedback compensation of the module.
page 13 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet recommended values of r tune and c tune for different output capacitor combinations are given in table 2. table 2 shows the recommended values of r tune and c tune for different values of ceramic output capacitors up to 1,000uf that might be needed for an application to meet output ripple and noise requirements. selecting r tune and c tune according to table 2 will ensure stable operation of the module. in applications with tight output voltage limits in the presence of dynamic current loading, additional output capacitance will be required. table 3 lists recommended values of r tune and c tune in order to meet 2% output voltage deviation limits for some common output voltages in the presence of a 10a to 40a step change (50% of full load), with an input voltage of 12v. please contact your fdk tec hnical representative to obtain more details of this feature as well as for guidelines on how to select the right value of external r-c to tune the module for best transient performance and stable operation for other output capacitance values. table 2: general recommended value of r tune and c tune for vin=12v and various external ceramic capacitor combinations. co 6x47uf 8x47uf 10x47uf 12x47uf 20x47uf r tune 330 ? 330 ? 330 ? 330 ? 200 ? c tune 330pf 820pf 1200pf 1500pf 3300pf table 3: recommended values of r tune and c tune to obtain transient deviation of 2% of vout for a 20a step load with vin=12v. vo 1.8v 1.2v 0.6v co 4x47uf+ 6x330uf polymer 4x47uf+ 11x330uf polymer 4x47uf+ 12x680uf polymer r tune 220 ? 200 ? 180 ? c tune 5600pf 12nf 47nf v 34mv 22mv 12mv note: the capacitors used in the tunable loop tables are 47 uf/3 m ? esr ceramic, 330 uf/12 m ? esr polymer capacitor and 680uf/12 m ? polymer capacitor. fig-10: circuit diagram showing connection of r tune and c tune to tune the control loop of the module.
page 14 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet digital feature description pmbus interface capability the 40a digital tomodachi power modules have a pmbus interface that supports both communication and control. the pmbus power management protocol specification can be obtained from www.pmbus.org. the modules support a subset of version 1.1 of the specification (see table 6 for a list of the specific commands supported). most module parameters can be programmed using pmbus and stored as defaults for later use. all communication over the module pmbus interface must support the packet error checking (pec) scheme. the pmbus master must generate the correct pec byte for all transactions, and check the pec byte returned by the module. the module also supports the smbalert# response protocol whereby the module can alert the bus master if it wants to talk. for more information on the smbus alert response protocol, see the system management bus (smbus) specification. the module has non-volatile memory that is used to store configuration settings. not all settings programmed into the device are automatically saved into this non-volatile memo ry, only those specifically identified as capable of being stored can be saved (see table 6 for which command parameters can be saved to non-volatile storage). pmbus data format for commands that set thresholds, voltages or report such quantities, the module supports the ?linear? data format among the three data formats supported by pmbus. the linear data format is a two byte value with an 11-bit, two?s complement mantissa and a 5-bit, two?s complement exponent. the format of the two data bytes is shown below: pmbus addressing the power module can be addressed through the pmbus using a device address. the module has 64 possible addresses (0 to 63 in decimal) which can be set using resistors connected from the addr0 and addr1 pins to sig_gnd. note that some of these addresses (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 12, 40, 44, 45, 55 in decimal) are reserved according to the smbus specifications and may not be useable. the address is set in the form of two octal (0 to 7) digits, with each pin setting one digit. the addr1 pin sets the high order digit and addr0 sets the low order digit. the resistor values suggested for each digit are shown in table 4 (1% tolerance resistors are recommended). note that if either address resistor value is outside the range specified in table 4, the module will respond to address 127. the user must know which i 2 c addresses are reserved in a system for special functions and set the address of the module to avoi d interfering with other system operations. both 100khz and 400khz bus speeds are supported by the module. connection for the pmbus interface should follow the high power dc specifications given in section 3.1.3 in the smbus specification v2.0 for the 400khz bus speed or the low power dc specifications in section 3.1.2. the complete smbus specification is available from the smbus web site, smbus.org . table 4: digit resistor value [k ? ] 0 10 1 15.4 2 23.7 3 36.5 4 54.9 5 84.5 6 130 7 200 data byte high 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 data byte low exponent msb mantissa msb the value is of the number is then given by value = mantissa x 2 exponent a ddr0 sig_gnd r addr0 r addr1 a ddr1 fig-11: circuit showing connection of resistors used to set the pmbus address of the module.
page 15 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet pmbus enabled on/off the module can also be turned on and off via the pmbus interface. the operation command is used to actually turn the module on and off via the pmbus, while the on_off_config command configures the combination of analog on/off pin input and pmbus commands needed to turn the module on and off. bit [7] in the operation command data byte enables the module, with the following functions: 0 : output is disabled 1 : output is enabled this module uses the lower five bits of the on_off_config data byte to set various on/off options as follows: bit position 4 3 2 1 0 access r/w r/w r/w r/w r function pu cmd cpr pol cpa default value 1 0 1 1 1 pu : sets the default to either operate any time input power is present or for the on/off to be controlled by the analog on/off input and the pmbus operation command. this bit is used together with the cp, cmd and on bits to determine startup. bit value a ction 0 module powers up any time power is present regardless of state of the analog on/off pin 1 module does not power up until commanded by the analog on/off pin and the operation command as programmed in bits [2:0] of the on_off_config register. cmd : the cmd bit controls how the device responds to the operation command. bit value a ction 0 module ignores the on bit in the operation command 1 module responds to the on bit in the operation command cpr : sets the response of the analog on/off pin. this bit is used together with the cmd, pu and on bits to determine startup. bit value a ction 0 module ignores the analog on/off pin, i.e. on/off is only controlled through the pmbus via the operation command 1 module requires the analog on/off pin to be asserted to start the unit pmbus adjustable soft start rise time the soft start rise time can be adjusted in the module via pmbus. when setting this parameter, make sure that the charging current for output capacitors can be delivered by the module in addition to any load current to avoid nuisance tripping of the overcurrent protection circuitry during startup. the ton_rise command sets the rise time in ms, and allows choosing soft start times between 600us and 9ms, with possible values listed in table 5. note that the exponent is fixed at -4 (decimal) and the upper two bits of the mantissa are also fixed at 0. table 5 rise time exponent mantissa 600us 11100 00000001010 900us 11100 00000001110 1.2ms 11100 00000010011 1.8ms 11100 00000011101 2.7ms 11100 00000101011 4.2ms 11100 00001000011 6.0ms 11100 00001100000 9.0ms 11100 00010010000 output voltage adjustment using the pmbus the vout_scale_loop parameter is important for a number of pmbus commands related to output voltage trimming, margining, over/under voltage protection and the pgood thresholds. the output voltage of the module is set as the combination of the voltage divider formed by rtrim and a 20k ? upper divider resistor inside the module, and the internal reference voltage of the module. the reference voltage v ref is nominally set at 600mv, and the output regulation voltage is then given by hence the module output voltage is dependent on the value of rtrim which is connected external to the module. the information on the output voltage divider ratio is conveyed to the module through the vout_scale_loop parameter which is calculated as follows: the vout_scale_loop parameter is specified using the ?linear? format and two bytes. the upper five bits [7:3] of the high byte are used to set the exponent which is fixed at ?9 (decimal). the remaining three bits of the high byte [2:0] and the rtrim rtrim loop scale vout ? ? 20000 _ _ ref out v rtrim rtrim v ? ? ? ? ? ? ? ? ? 20000
page 16 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet eight bits of the lower byte are used for the mantissa. the default value of the mantissa is 00100000000 corresponding to 256 (decimal), corresponding to a divider ratio of 0.5. the maximum value of the mantissa is 512 corresponding to a divider ratio of 1. note that the resolution of the vout_scale_loop command is 0.2%. when pmbus commands are used to trim or margin the output voltage, the value of v ref is what is changed inside the module, which in turn changes the regulated output voltage of the module. the nominal output voltage of the module can be adjusted with a minimum step size of 0.4% over a 25% range from nominal using the vout_trim command over the pmbus. the vout_trim command is used to apply a fixed offset voltage to the output voltage command value using the ?linear? mode with the exponent fixed at ? 10 (decimal). the value of the offset voltage is given by this offset voltage is added to the voltage set through the divider ratio and nominal vref to produce the trimmed output voltage. the valid range in two?s complement for this command is ?4000h to 3999h. the high order two bits of the high byte must both be either 0 or 1. if a value outside of the +/-25% adjustment range is given with this command, the module will set it?s output voltage to the nominal value (as if vout_trim had been set to 0), assert smbalrt#, set the cml bit in status_byte and the invalid data bit in status_cml. output voltage margining using the pmbus the module can also have its output voltage margined via pmbus commands. the command vout_margin_high sets the margin high voltage, while the command vout_margin_low sets the margin low voltage. both the vout_margin_high and vout_margin_low commands use the ?linear? mode with the exponent fixed at ?10 (decimal). two bytes are used for the mantissa with the upper bit [7] of the high byte fixed at 0. the actual margined output voltage is a combination of the vout_margin_high or vout_margin_low and the vout_trim values as shown below. note that the sum of the margin and trim voltages cannot be outside the 25% window around the nominal output voltage. the data associated with vout_margin_high and vout_margin_low can be stored to non-volatile memory using the store_default_all command. the module is commanded to go to the margined high or low voltages using the operation command. bits [5:2] are used to enable margining as follows: 00xx : margin off 0101 : margin low (ignore fault) 0110 : margin low (act on fault) 1001 : margin high (ignore fault) 1010 : margin high (act on fault) pmbus adjustable overcurrent warning the module can provide an overcurrent warning via the pmbus. the threshold for the overcurrent warning can be set using the parameter iout_oc_warn_limit. this command uses the ?linear? data format with a two byte data word where the upper five bits [7:3] of the high byte represent the exponent and the remaining three bits of the high byte [2:0] and the eight bits in the low byte represent the mantissa. the exponent is fi xed at ?1 (decimal). the upper five bits of the mantissa are fixed at 0 while the lower six bits are programmable with a default value of 55.5a (decimal). the resolution of this warning limit is 500ma. the value of the iout_oc_warn_limit can be stored to non-volatile memory using the store_default_all command. temperature status via pmbus the module can provide information related to temperature of the module through the status_temperature command. the command returns information about whether the pre-set over temperature fault thres hold and/or the warning threshold have been exceeded. pmbus adjustable output over and under voltage protection the module has output over and under voltage protection capability. the pmbus command vout_ov_fault_limit is used to set the output over voltage threshold from four possible values: 108%, 110%, 112% or 115% of the commanded output voltage. the command vout_uv_fault_limit sets the threshold that causes an output under voltage fault and can also be selected from four possible values: 92%, 90%, 88% or 10 ) ( 2 _ ? ? ? trim vout v offset out 10 ) ( 2 ) _ _ _ ( ? ? ? ? trim vout high margin vout v mh out 10 ) ( 2 ) _ _ _ ( ? ? ? ? trim vout low margin vout v ml out
page 17 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet 85%. the default values are 112% and 88% of commanded output voltage. both commands use two data bytes formatted as two?s complement binary integers. the ?linear? mode is used with the exponent fixed to ?10 (decimal) and the effective over or under voltage trip points given by: values within the supported range for over and undervoltage detection thresholds will be set to the nearest fixed percentage. note that the correct value for vout_scale_loop must be set in the module for the correct over or under voltage trip points to be calculated. in addition to adjustable output voltage protection, the 40a digital tomodachi module can also be programmed for the response to the fault. the vout_ov_fault_response and vout_uv_fault_respon se commands specify the response to the fault. both these commands use a single data byte with the possible options as shown below. 1. continue operation without interruption (bits [7:6] = 00, bits [5:3] = xxx) 2. continue for four switching cycles and then shut down if the fault is still present, followed by no restart or continuous restart (bits [7:6] = 01, bits [5:3] = 000 means no restart, bits [5:3] = 111 means continuous restart) 3. immediate shut down followed by no restart or continuous restart (bits [7:6] = 10, bits [5:3] = 000 means no restart, bits [5:3] = 111 means continuous restart). 4. module output is disabled when the fault is present and the output is enabled when the fault no longer exists (bits [7:6] = 11, bits [5:3] = xxx). note that separate respon se choices are possible for output over voltage or under voltage faults. pmbus adjustable input undervoltage lockout the module allows adjustment of the input under voltage lockout and hysteresis. the command vin_on allows setting the input voltage turn on threshold, while the vin_off command sets the input voltage turn off threshold. for the vin_on command, possible values are 3.5v to 14v in 0.5v steps. for the vin_off command, possible values are 3v to 14v in 0.5v steps. if other values are entered for either command, they will be mapped to the closest of the allowed values. both the vin_on and vin_off commands use the ?linear? format with two data bytes. the upper five bits represent the expon ent (fixed at -2) and the remaining 11 bits represent the mantissa. for the mantissa, the four most significant bits are fixed at 0. power good the module provides a power good (pgood) signal that is implemented with an open-drain output to indicate that the output voltage is within the regulation limits of the power module. the pgood signal will be de-asserted to a low state if any condition such as overtemperature, overcurr ent or loss of regulation occurs that would result in the output voltage going outside the specified thresholds. the pgood thresholds are user selectable via the pmbus (the default values are as shown in the feature specifications section). each threshold is set up symmetrically above and below the nominal value. the power_good_on command sets the output voltage level above which pgoo d is asserted (lower threshold). for example, with a 1.2v nominal output voltage, the power_good_on threshold can set the lower threshold to 1.14 or 1.1v. doing this will automatically set the upper thre sholds to 1.26 or 1.3v. the power_good_off command sets the level below which the pgood command is de-asserted. this command also sets tw o thresholds symmetrically placed around the nominal output voltage. normally, the power_good_on threshold is set higher than the power_good_off threshold. both power_good_on and power_good_off commands use the ?linear? format with the exponent fixed at ?10 (decimal). the two thresholds are given by both commands use two data bytes with bit [7] of the high byte fixed at 0, while the remaining bits are r/w and used to set the mantissa using two?s complement representation. both commands also use the vout_scale_loop parameter so it must be set correctly. the default value of power_good_on is set at 1.1035v and that of the power_good_off is set at 1.08v. the values associated with these commands can be stored in non-volatile memory using the store_default_all command. the pgood terminal can be connected through a pullup resistor (suggested value 100k ? ) to a source of 5vdc or lower. 10 ) _ ( 10 ) _ ( 2 ) _ _ _ ( 2 ) _ _ _ ( ? ? ? ? ? ? limit fault uv vout v limit fault ov vout v req uv out req ov out 10 ) _ ( 10 ) _ ( 2 ) _ _ ( 2 ) _ _ ( ? ? ? ? ? ? off good power v on good power v off pgood out on pgood out
page 18 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet measurement of output current, output voltage and input voltage the module is capable of measuring key module parameters such as output current and voltage and input voltage and providing this information through the pmbus interface. roughly every 200us, the module makes 16 measurements each of output current, voltage and input voltage. average values of of these 16 measurements are then calculated and placed in the appropriate regi sters. the values in the registers can then be read us ing the pmbus interface. measuring output curr ent using the pmbus the module measures current by using the inductor winding resistance as a current sense element. the inductor winding resistance is then the current gain factor used to scale the measured voltage into a current reading. this gain factor is the argument of the iout_cal_gain command, and consists of two bytes in the linear data format. the exponent uses the upper five bits [7:3] of the high data byte in two-s complement format and is fixed at ?15 (decimal). the remaining 11 bits in two?s complement binary format represent the mantissa. during manufacture, each module is calibrated by measuring and storing the current gain factor into non-volatile storage. the current measurement accu racy is also improved by each module being calibrated during manufacture with the offset in the current reading. the iout_cal_offset command is used to store and read the current offset. the argument for this command consists of two bytes composed of a 5-bit exponent (fixed at -4d) and a 11-bit mantissa. this command has a resolution of 62.5ma and a range of -4000ma to +3937.5ma. the read_iout command provides module average output current information. this command only supports positive or current sourced from the module. if the converter is sinking current a reading of 0 is provided. the read_iout command returns two bytes of data in the linear data format. the exponent uses the upper five bits [7:3] of the high data byte in two-s complement format and is fixed at ?4 (decimal). the remaining 11 bits in two?s complement binary format represent the mantissa with the 11 th bit fixed at 0 since only positive numbers are considered valid. note that the current reading provided by the module is not corrected for temperature. the temperature corrected current reading for module temperature t module can be estimated using the following equation. where i out_corr is the temperature corrected value of the current measurement, i read_out is the module current measurement value, t ind is the temperature of the inductor winding on the module. since it may be difficult to measure t ind , it may be approximated by an estimate of the module temperature. measuring output vo ltage using the pmbus the module can provide output voltage information using the read_vout command. the command returns two bytes of data all representing the mantissa while the exponent is fixed at -10 (decimal). during manufacture of the module, offset and gain correction values are written into the non-volatile memory of the module. the command vout_cal_offset can be used to read and/or write the offset (two bytes consisting of a 16-bit mantissa in two?s complement format) while the exponent is always fixed at -10 (decimal). the allowed range for this offset correction is -125 to 124mv. the command vout_cal_gain can be used to read and/or write the gain correction - two bytes consisting of a five-bit exponent (fixed at -8) and a 11-bit mantissa. the range of this correction factor is -0.125v to +0.121v, with a resolution of 0.004v. the corrected output voltage reading is then given by: measuring input voltage using the pmbus the module can provide output voltage information using the read_vin command. the command returns two bytes of data in the linear format. the upper five bits [7:3] of the high data form the two?s complement representation of the mantissa which is fixed at ?5 (decimal). the remaining 11 bits are used for two?s complement representation of the mantissa, with the 11 th bit fixed at zero since only positive numbers are valid. during module manufacture, offset and gain correction values are written into the non-volatile memory of the module. the command vin_cal_offset can be used to read and/or write the offset - two bytes consisting of a five-bit exponent (fixed at -5) and a 11-bit mantissa in two?s complement format. the allowed range for this offset correction is -2 to 1.968v, and the resolution is 32mv. the command vin_cal_gain can be used to read and/or write the gain correction - two bytes consisting of a five-bit exponent (f ixed at -8) and a 11-bit mantissa. the range of this correction factor is offset cal vout gain cal vout initial v final v out out _ _ )] _ _ 1 ( ) ( [ ) ( ? ? ? ? ] 00393 . 0 ) 30 [( 1 _ , ? ? ? ? ind out read corr out t i i
page 19 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet -0.125v to +0.121v, with a resolution of 0.004v. the corrected output voltage reading is then given by: reading the status of the module using the pmbus the module supports a number of pmbus status information commands. however, not all features are supported in these commands. a 1 in the bit position indicates the fault that is flagged. status_byte : returns one byte of information with a summary of the most critical device faults. bit position flag default value 7 x 0 6 off 0 5 vout overvoltage 0 4 iout overcurrent 0 3 vin undervoltage 0 2 temperature 0 1 cml (comm. memory fault) 0 0 none of the above 0 status_word : returns two bytes of information with a summary of the module?s fault/warning conditions. low byte bit position flag default value 7 x 0 6 off 0 5 vout overvoltage 0 4 iout overcurrent 0 3 vin undervoltage 0 2 temperature 0 1 cml (comm. memory fault) 0 0 none of the above 0 high byte bit position flag default value 7 vout fault or warning 0 6 iout fault or warning 0 5 x 0 4 x 0 3 power_good# (is negated) 0 2 x 0 1 x 0 0 x 0 status_vout : returns one byte of information relating to the status of the module?s output voltage related faults. status_iout : returns one byte of information relating to the status of the module?s output voltage related faults. bit position flag default value 7 iout oc fault 0 6 x 0 5 iout oc warning 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 status_temperature : returns one byte of information relating to the status of the module?s temperature related faults. bit position flag default value 7 ot fault 0 6 ot warning 0 5 x 0 4 x 0 3 x 0 2 x 0 1 x 0 0 x 0 status_cml : returns one byte of information relating to the status of the module?s communication related faults. bit position flag default value 7 invalid/unsupported command 0 6 invalid/unsupported command 0 5 packet error check failed 0 4 x 0 bit position flag default value 7 vout ov fault 0 6 x 0 5 x 0 4 vout uv fault 0 3 x 0 2 x 0 1 x 0 0 x 0 offset cal vin gain cal vin initial v final v in in _ _ )] _ _ 1 ( ) ( [ ) ( ? ? ? ?
page 20 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet 3 x 0 2 x 0 1 other communication fault 0 0 x 0 mfr_vin_min : returns minimum input voltage as two data bytes of informati on in linear format (upper five bits are exponent ? fixed at -2, and lower 11 bits are mantissa in two?s complement format ? fixed at 12) mfr_vout_min : returns minimum output voltage as two data bytes of information in linear format (upper five bits are exponent ? fixed at -10, and lower 11 bits are mantissa in two?s complement format ? fixed at 614) mfr_specific_00 : returns information related to the type of module. bits [7:2] in the low byte indicate the module type (000100 corresponds to the fgld12sr6040 series of module). bit 1:0 in the high byte are used to indicate the manufacturer id, with 01 reserved for fdk. low byte bit position flag default value 7:2 module name 000100 1:0 reserved 10 high byte bit position flag default value 7:0 reserved none 1:0 manufacturer id 01
page 21 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet summary of supported pmbus commands please refer to the pmbus 1.1 specificati on for more details of these commands. table 6 hex code command brief description non-volatile memory storage 01 operation turn module on or off. also used to margin the output voltage format unsigned binary bit position 7 6 5 4 3 2 1 0 access r/w r r/w r/w r/w r/w r r function on x margin x x default value 0 0 0 0 0 0 x x 02 on_off_config configures the on/off functionality as a combination of analog on/off pin and pmbus commands format unsigned binary bit position 7 6 5 4 3 2 1 0 access r r r r/w r/w r/w r/w r function x x x pu cmd cpr pol cpa default value 0 0 0 1 0 1 1 1 yes 03 clear_faults clear any fault bits that may have been set, also releases the smbalert# signal if the device has been asserting it. 10 write_protect used to control writing to the module vi a pmbus. copies the current register setting in the module whose command code matches the value in the data byte into non-volatile memory (eeprom) on the module format unsigned binary bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w x x x x x function bit7 bit6 bit5 x x x x x default value 0 0 0 x x x x x bit5: 0 ? enables all writes as permitted in bit6 or bit7 1 ? disables all writes ex cept the write_protect, operation and on_off_config (bit 6 and bit7 must be 0) bit 6: 0 ? enables all writes as permitted in bit5 or bit7 1 ? disables all writes except for the write_protect and operation commands (bit5 and bit7 must be 0) bit7: 0 ? enables all writes as permitted in bit5 or bit6 1 ? disables all writes except for the write_protect command (bit5 and bit6 must be 0) yes 11 store_default_all copies all current register settings in the module into non-volatile memory (eeprom) on the module. takes about 50ms for the command to execute. 12 restore_default_all restores all current register settings in the module from values in the module non-volatile memory (eeprom) 13 store_default_code copies the current register setting in the module whose command code matches the value in the data byte in to non-volatile memory (eeprom) on the module bit position 7 6 5 4 3 2 1 0 access w w w w w w w w function command code 14 restore_default_code restores the current register setting in the module whose command code matches the value in the data byte from the value in the module non-volatile memory (eeprom) bit position 7 6 5 4 3 2 1 0 access w w w w w w w w function command code 20 vout_mode the module has mode set to linear and exponent set to -10. these values cannot be changed bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function mode exponent default value 0 0 0 1 0 1 1 0
page 22 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet table 6 (continued) hex code command brief description non-volatile memory storage 22 vout_trim apply a fixed offset voltage to the output voltage command value. exponent is fixed at -10. format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function high byte default value 0 0 0 0 0 0 0 0 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function low byte default value 0 0 0 0 0 0 0 0 yes 25 vout_margin_high sets the target voltage for margining the output high. exponent is fixed at -10. format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r/w r/w r/w r/w r/w r/w r/w function high byte default value 0 0 0 0 0 1 0 1 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function low byte default value 0 1 0 0 0 1 1 1 yes 26 vout_margin_low sets the target voltage for margining the output low. exponent is fixed at -10 format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r/w r/w r/w r/w r/w r/w r/w function high byte default value 0 0 0 0 0 1 0 0 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function low byte default value 0 1 0 1 0 0 0 1 yes 29 vout_scale_loop sets the scaling of the output voltage ? equal to the feedback resistor divider ratio format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r/w r/w function exponent mantissa default value 1 0 1 1 1 0 0 1 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function mantissa default value 0 0 0 0 0 0 0 0 yes 35 vin_on sets the value of input voltage at which the module turns on format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function exponent mantissa default value 1 1 1 1 0 0 0 0 bit position 7 6 5 4 3 2 1 0 access r r/w r/w r/w r/w r/w r/w r/w function mantissa default value 0 0 0 0 1 1 1 0 yes
page 23 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet table 6 (continued) hex code command brief description non-volatile memory storage 36 vin_off sets the value of input voltage at which the module turns off format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function exponent mantissa default value 1 1 1 1 0 0 0 0 bit position 7 6 5 4 3 2 1 0 access r r/w r/w r/w r/w r/w r/w r/w function mantissa default value 0 0 0 0 1 1 0 0 yes 38 iout_cal_gain returns the value of the gain correction term used to correct the measured output current format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r/w function exponent mantissa default value 1 0 0 0 1 0 0 0 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function mantissa default value v: variable based on factory calibration yes 39 iout_cal_offset returns the value of the offset correction term used to correct the measured output current format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r/w r r function exponent mantissa default value 1 1 1 0 0 1 1 1 bit position 7 6 5 4 3 2 1 0 access r r r/w r/w r/w r/w r/w r/w function mantissa default value v: variable based on factory calibration yes 40 vout_ov_fault_limit sets the voltage level for an output overvoltage fault. exponent is fixed at -10. format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r/w r/w r/w r/w r/w r/w r/w function high byte default value 0 0 0 0 0 1 0 1 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function low byte default value 0 0 0 0 1 0 1 0 yes 41 vout_ov_fault_response instructs the module on what action to take in response to a output overvoltage fault format unsigned binary bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r r r function rsp [1] rsp [0] rs[2] rs[1] rs[0] x x x default value 1 1 1 1 1 1 0 0 yes
page 24 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet table 6 (continued) hex code command brief description non-volatile memory storage 44 vout_uv_fault_limit sets the voltage level for an output undervoltage fault. exponent is fixed at -10. format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r/w r/w r/w r/w r/w r/w r/w function high byte default value 0 0 0 0 0 1 0 0 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function low byte default value 1 0 0 0 1 1 1 1 yes 45 vout_uv_fault_response instructs the module on what action to take in response to a output undervoltage fault format unsigned binary bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r r r function rsp [1] rsp [0] rs[2] rs[1] rs[0] x x x default value 0 0 0 0 0 1 0 0 yes 46 iout_oc_fault_limit sets the output overcurrent fault level in a (cannot be changed) format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function exponent mantissa default value 1 1 1 1 1 0 0 0 bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function mantissa default value 0 1 1 1 0 1 0 0 yes 4a iout_oc_warn_limit sets the output overcurrent warning level in a format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function exponent mantissa default value 1 1 1 1 1 0 0 0 bit position 7 6 5 4 3 2 1 0 access r r/w r/w r/w r/w r/w r/w r/w function mantissa default value 0 1 1 1 0 0 1 0 yes 5e power_good_on sets the output voltage level at which the pgood pin is asserted high. exponent is fixed at -10. format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r/w r/w r/w r/w r/w r/w r/w function high byte default value 0 0 0 0 0 1 0 0 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function low byte default value 0 1 1 0 1 0 1 0 yes
page 25 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet table 6 (continued) hex code command brief description non-volatile memory storage 5f power_good_off sets the output voltage level at which the pgood pin is de-asserted low. exponent is fixed at -10. format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r/w r/w r/w r/w r/w r/w r/w function high byte default value 0 0 0 0 0 1 0 0 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function low byte default value 0 1 0 1 0 0 1 0 yes 61 ton_rise sets the rise time of the output voltage during startup format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r/w function exponent mantissa default value 1 1 1 0 0 0 0 0 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function mantissa default value 0 0 1 0 1 0 1 0 yes 78 status_byte returns one byte of information with a summary of the most critical module faults format unsigned binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r flag x off vout _ov iout _oc vin_ uv temp cml othe r default value 0 0 0 0 0 0 0 0 79 status_word returns two bytes of information with a summary of the module?s fault/warning conditions format unsigned binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r flag vout iout _oc x x pgo od x x x default value 0 0 0 0 0 0 0 0 bit position 7 6 5 4 3 2 1 0 access r r r r r r r r flag x off vout _ov iout _oc vin_ uv temp cml othe r default value 0 0 0 0 0 0 0 0 7a status_vout returns one byte of information with the status of the module?s output voltage related faults format unsigned binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r flag vout_ov x x vout_uv x x x x default value 0 0 0 0 0 0 0 0 7b status_iout returns one byte of information with the status of the module?s output current related faults format unsigned binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r flag iout_oc x x x iout_oc_warn x x x default value 0 0 0 0 0 0 0 0
page 26 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet table 6 (continued) hex code command brief description non-volatile memory storage 7d status_temperature returns one byte of information with the status of the module?s temperature related faults format unsigned binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r flag ot_fault ot_warn x x x x x x default value 0 0 0 0 0 0 0 0 7e status_cml returns one byte of information with the status of the module?s communication related faults format unsigned binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r flag invalid command invalid data pec fail xxx other comm fault x default value 0 0 0 0 0 0 0 0 88 read_vin returns the value of the input voltage applied to the module format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function exponent mantissa default value 1 1 0 1 1 0 0 0 bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function mantissa default value 0 0 0 0 0 0 0 0 8b read_vout returns the value of the output voltage of the module. exponent is fixed at -10. format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function mantissa default value 0 0 0 0 0 0 0 0 bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function mantissa default value 0 0 0 0 0 0 0 0 8c read_iout returns the value of the output current of the module format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function exponent mantissa default value 1 1 1 0 0 0 0 0 bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function mantissa default value 0 0 0 0 0 0 0 0 98 pmbus_revision returns one byte indicating the module is compliant to pmbus spec. 1.1 (read only) format unsigned binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r default value 0 0 0 1 0 0 0 1 yes
page 27 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet table 6 (continued) hex code command brief description non-volatile memory storage a0 mfr_vin_min returns the minimum input voltage the m odule is specified to operate at (read only) format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function exponent mantissa default value 1 1 1 1 0 0 0 0 bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function mantissa default value 0 0 0 0 1 1 0 0 yes a4 mfr_vout_min returns the minimum output voltage possible from the module (read only) format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function mantissa default value 0 0 0 0 0 0 1 0 bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function mantissa default value 0 1 1 0 0 1 1 0 yes d0 mfr_specific_00 returns module name information (read only) format unsigned binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function reserved default value 0 0 0 0 0 0 0 0 bit position 7 6 5 4 3 2 1 0 access r r r r r r r r function module name reserved default value 0 0 0 1 0 0 0 0 yes d4 vout_cal_offset applies an offset to the read_vout command results to calibrate out offset errors in module measurements of the output voltage (between -125mv and +124mv). exponent is fixed at -10. format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r/w r r r r r r r function mantissa default value v 0 0 0 0 0 0 0 bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function mantissa default value v v v v v v v v yes d5 vout_cal_gain applies a gain correction to the read_vout command results to calibrate out gain errors in module measurements of the output voltage (between -0.125 and 0.121) format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r r r r/w function exponent mantissa default value 1 1 0 0 0 0 0 v bit position 7 6 5 4 3 2 1 0 access r/w r/w r/w r/w r/w r/w r/w r/w function mantissa default value v v v v v v v v yes
page 28 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet table 6 (continued) hex code command brief description non-volatile memory storage d6 vin_cal_offset applies an offset correction to the read_vin command results to calibrate out offset errors in module measurements of the input voltage (between -2v and +1.968v) format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r/w r r r/w function exponent mantissa default value 1 1 0 1 v 0 0 v bit position 7 6 5 4 3 2 1 0 access r r r/w r/w r/w r/w r/w r/w function mantissa default value 0 0 v v v v v v yes d7 vin_cal_gain applies a gain correction to the read_vin command results to calibrate out gain errors in module measurements of the input voltage (between -0.125 and 0.121) format linear, two?s complement binary bit position 7 6 5 4 3 2 1 0 access r r r r r/w r r r/w function exponent mantissa default value 1 1 0 0 v 0 0 v bit position 7 6 5 4 3 2 1 0 access r r r r/w r/w r/w r/w r/w function mantissa default value 0 0 0 v v v v v yes
page 29 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet characterization overview the converter has been characterized for several operational features, including efficiency, thermal derating (maximum available load current as a function of ambient temperature and airflow), ripple and noise, transient response to load step changes, start-up and shutdown characteristics. figures showing data plots and waveforms for different output voltages are presented in the following pages. thermal considerations power modules operate in a variety of thermal environments; however, sufficient cooling should always be provided to help ensure reliable operation. considerations include ambient temperature, airflow, module power dissipation, and the need for increased reliability. a reduction in the operating temperature of the module will result in an increase in reliability. the thermal data presented here is based on physical measurements taken in a wind tunnel. the test set-up is shown in fig-12. the preferred airflow direction for the module is in fig-13. the maximum available load current, for any given set of conditions, is defined as the lower of: (i) the output current at wh ich the temperature of any component reaches 120c, or (ii) the current rating of the converter (40a) a maximum component temperature of 120c should not be exceeded in order to operate within the derating curves. thus, the temperature at the thermocouple location shown in fig-13 should not exceed 120c in normal operation. note that continuous operation beyond the derated current as specified by the derating curves may lead to degradation in performance and reliability of the converter and may result in permanent damage. air flow x power module w ind tunnel pwbs 12.7_ (0.50) 76.2_ (3.0) probe location for measuring airflow and ambient temperature 25.4_ (1.0) fig-12: thermal test set-up fig-13: preferred airflow direction and location of hot-spot of the module (tref).
page 30 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet characteristic curves the following figures provide typical characteristics for the 40a digital tomodachi at 1.8vo and 25c efficiency, ? (%) output current, io (a) output current, io (a) ambient temperature, ta oc fig-14. converter efficiency versus output current. fig-15. derating output current versus ambient temperature and airflow. output voltage vo (v) (20mv/div) output current, output voltage io (a) (20adiv) vo (v) (20mv/div) time, t (1us/div) time, t (20us /div) fig-16. typical output ripple and noise (co=6x47uf ceramic, vin = 12v, io = io,max, ). fig-17. transient response to dynamic load change from 50% to 100% at 12vin, cout=6x330uf, ctune=5.6nf & rtune=220 ohms output voltage on/off voltage vo (v) (500mv/div) von/off (v) (5v/div) output voltage input voltage vo (v) (500mv/div) vin (v) (5v/div) time, t (1ms/div) time, t (1ms/div) fig-18. typical start-up using on/off voltage (io = io,max). fig-19. typical start-up usin g input voltage (vin = 12v, io = io,max). 70 75 80 85 90 95 100 0 10 20 30 40 vin=14.4v vin=12v vin=4.5v 5 10 15 20 25 30 35 40 45 45 55 65 75 85 95 105 2m/s (400lfm) 1.5m/s 1m/s (200lfm) 0.5m/s (100lfm) nc standard part (85c) ruggedized (d) part (105c)
page 31 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet characteristic curves the following figures provide typical characteristics for the 40a digital tomodachi at 1.2vo and 25c efficiency, ? (%) output current, io (a) output current, i o (a) ambient temperature, t a o c fig-20. converter efficiency versus output current. fig-21. derating output current versus ambient temperature and airflow. output voltage v o (v) (10mv/div) output current, output voltage i o (a) (20adiv) v o (v) (20mv/div) time, t (1us/div) time, t (20us /div) fig-22. typical output ripple and noise (co=6x47uf ceramic, vin = 12v, io = io,max, ). fig-23. transient response to dynamic load change from 50% to 100% at 12vin, cout=6x330uf, ctune=12nf & rtune=200 ohms output voltage on/off voltage v o (v) (500mv/div) v on/off (v) (5v/div) output voltage input voltage v o (v) (500mv/div) v in (v) (5v/div) time, t (1ms/div) time, t (1ms/div) fig-24. typical start-up using on/off voltage (io = io,max). fig-25. typical start-up using input voltage (vin = 12v, io = io,max). 70 75 80 85 90 95 0 10203040 vin=14.4v vin=12v vin=4.5v 10 15 20 25 30 35 40 45 45 55 65 75 85 95 105 2m/s (400lfm) 1.5m/s (300lfm) 1m/s (200lfm) 0.5m/s (100lfm) nc standard part (85c) ruggedized (d) part (105c)
page 32 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet characteristic curves the following figures provide typical characteristics for the 40a digital tomodachi at 0.6vo and 25c efficiency, ? (%) output current, io (a) output current, i o (a) ambient temperature, t a o c fig-26. converter efficiency versus output current. fig-27. derating output current versus ambient temperature and airflow. output voltage v o (v) (10mv/div) output current, output voltage i o (a) (10adiv) v o (v) (5mv/div) time, t (1us/div) time, t (20us /div) fig-28. typical output ripple and noise (co=6x47uf ceramic, vin = 12v, io = io,max, ). fig-29. transient response to dynamic load change from 50% to 100% at 12vin, cout=12x680uf+6x47uf, ctune=47uf, rtune=180 ohms output voltage on/off voltage v o (v) (200mv/div) v on/off (v) (5v/div) output voltage input voltage v o (v) (200mv/div) v in (v) (5v/div) time, t (1ms/div) time, t (1ms/div) fig-30. typical start-up using on/off voltage (io = io,max). fig-31. typical start-up usin g input voltage (vin = 12v, io = io,max). 70 75 80 85 90 0 10203040 vin=14v vin=12v vin=4.5v 15 20 25 30 35 40 45 45 55 65 75 85 95 105 2m/s (400lfm) 1.5m/s ( 300lfm ) 0.5m/s (100lfm) nc ruggedized (d) part (105c) standard part (85c) 1m/s ( 200lfm )
page 33 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet example application circuit requirements: vin: 12v vout: 1.8v iout: 30a max., worst case load transient is from 20a to 30a ? vout: 1.5% of vout (27mv) for worst case load transient vin, ripple 1.5% of vin (180mv, p-p) ci1 decoupling cap - 1x0.01uf/16v ceramic capacitor (e.g. murata lll185r71e103ma01) ci2 3x22uf/16v ceramic capacitor (e.g. murata grm32er61c226ke20) ci3 470uf/16v bulk electrolytic co2 4x47uf/6.3v ceramic capacitor (e.g. murata grm31cr60j476me19) co3 6x330uf/6.3v polymer (e.g. sanyo poscap) ctune 5600pf ceramic capacitor (can be 1206, 0805 or 0603 size) rtune 220 ? smt resistor (can be 1206, 0805 or 0603 size) rtrim 10k ? smt resistor (can be 1206, 0805 or 0603 size, recommended tolerance of 0.1%) note: the data, clk and smbalrt pins do not have any pull-up resistors inside the module. typically, the smbus master controller will have the pull-up r esistors as well as provide the driving source for these signals. raddr0 data cl k vs- raddr1 gnd vin+ ci3 co3 addr0 vout vs+ gnd trim ctune rtune rtrim vin co1 ci1 vout+ on/off seq smbalrt# module pgood addr1 sig_gnd syn ci2 co2 share
page 34 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet mechanical drawing all dimensions are in millimeters (inches) tolerances: x.x mm ? 0.5 mm (x.xx in. ? 0.02 in.) [unless otherwise indicated] x.xx mm ? 0.25 mm (x.xxx in ? 0.010 in.) pin connections pin # function pin # function 1 on/off 11 sig_gnd 2 vin 12 vs- 3 seq 13 clk 4 gnd 14 data 5 vout 15 sync 6 trim 16 pg 7 vs+ 17 smbalert# 8 gnd 18 address 0 9 share 19 address 1 10 gnd bottom ? view 19 18 17 16 2 8 15 3 4 5 6 7 9 12 13 14 10 11 1 side view
page 35 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet recommended pad layout all dimensions are in millimeters (inches) tolerances: x.x mm ? 0.5 mm (x.xx in. ? 0.02 in.) [unless otherwise indicated] x.xx mm ? 0.25 mm (x.xxx in ? 0.010 in.) pin connections pin # function pin # function 1 on/off 11 sig_gnd 2 vin 12 vs- 3 seq 13 clk 4 gnd 14 data 5 vout 15 sync 6 trim 16 pg 7 vs+ 17 smbalert# 8 gnd 18 address 0 9 share 19 address 1 10 gnd
page 36 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet packaging details the 40a digital tomodachi modules are supplied in tape & reel as standard. modules are shipped in quantities of 140 modules per reel. all dimensions are in m illimeters and (in inches). reel dimensions: outside dimensions: 330.2 mm (13.00 ?) inside dimensions: 177.8 mm (7.00?) tape width: 56.00 mm (2.205?)
page 37 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet surface mount information pick and place the 40a digital tomodachi modules use an open frame construction and are designed for a fully automated assembly process. the modules are fitted with a label designed to provide a large surface area for pick and place operations. the label meets all the requirements for surface mount processing, as well as safety standards, and is able to withstand reflow temperatures of up to 300c. the label also carries product information such as product code, serial number and the location of manufacture. nozzle recommendations the module weight has been kept to a minimum by using open frame construction. variables such as nozzle size, tip style, vacuum pressure and placement speed should be considered to optimize this process. the minimum recommended inside nozzle diameter for reliable operation is 3mm. the maximum nozzle outer diameter, which will safely fit within the allowable component spacing, is 7mm. bottom side / first side assembly this module is not recommended for assembly on the bottom side of a customer board. if such an assembly is attempted, components may fall off the module during the second reflow process. lead free soldering the modules are lead-free (pb-free) and rohs compliant and fully compatible in a pb-free soldering process. failure to observe the instructions below may result in the failure of or cause damage to the modules and can adversely affect long-term reliability. pb-free reflow profile power systems will comply with j-std-020 rev. c (moisture / reflow sensitivity classification for nonhermetic solid state surface mount devices) for both pb-free solder profiles and msl classification procedures. this standard provides a recommended forced-air-convection reflow profile based on the volume and thickness of t he package (table 4-2). the suggested pb-free solder paste is sn/ag/cu (sac). the recommended linear reflow profile using sn/ag/cu solder is shown in fig-51. soldering outside of the recommended profile requires testing to verify results and performance. msl rating the 40a digital tomodachi modules have a msl rating of 2a. storage and handling the recommended storage environment and handling procedures for moisture-sensitive surface mount packages is detailed in j-std-033 rev. a (handling, packing, shipping and use of moisture/reflow sensitive surface mount de vices). moisture barrier bags (mbb) with desiccant are required for msl ratings of 2 or greater. these sealed packages should not be broken until time of use. once the original package is broken, the floor life of the product at conditions of ? 30c and 60% relative humidity varies according to the msl rating (see j-std-033a). the shelf life for dry packed smt packages will be a minimum of 12 months from the bag seal date, when stored at the following co nditions: < 40c, < 90% relative humidity. post solder cleaning and drying considerations post solder cleaning is usually the final circuit-board assembly process prior to electrical board testing. the result of inadequate cleaning and drying can affect both the reliability of a power module and the testability of the finished circuit-board assembly. for guidance on appropriate soldering, cleaning and drying procedures, refer to board mounted power modules: soldering and cleaning application note (an04-001). per j-std-020 rev. c 0 50 100 150 200 250 300 reflow time (seconds) reflow temp (c) heating zone 1c/second peak temp 260c * min. time above 235c 15 seconds *time above 217c 60 seconds cooling zone fig-32: recommended linear reflow profile using sn/ag/cu solder.
page 38 of 38 delivering next generation technology series fgld12sr6040*a 4.5-14.4vdc input, 40a, 0.45-2.0vdc output http://www.fdk.com ver 1.6 apr. 24, 2013 preliminary data sheet part number system product series shape regulation input voltage mounting scheme output voltage rated current on/off logic pin shape fg l d 12 s r60 40 * a series name large d: digital feature typ=12v surface mount 0.6v (programmable: see page 9) 40a n: negative p: positive standard cautions nuclear and medical applications: fdk corporation products are not authorize d for use as critical components in life support systems, equipment used in hazardous environm ents, or nuclear control systems without the written consent of fdk corporation. specification changes and revisions: specifications are version- controlled, but are subject to change without notice.

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